See the previous published edition.
Welcome to the twenty-second issue of the MLIR (bi)Weekly, a newsletter (published on Friday) covering developments in MLIR, and related projects in the ecosystem. MLIR (bi)Weekly is brought to you by a collective effort of contributors, we welcome your contributions!
Highlights
- Some Updates on MLIR based Dynamic Shape Compiler - #13 by linearhit were shared with exciting preliminary results!
MLIR Core
Infrastructure
- PDL rewrite patterns are now supported by PatternApplicator, meaning that PDL is now connected end-to-end.
- The PassManager can now run on operations other than ModuleOp.
- The parser is no longer hardcoded to parse a ModuleOp, and can now parse other container operations or directly into a provided Block.
- Several improvements to operation parser/printers:
- The custom operation assembly format now properly supports optional enum attributes.
- Newlines are now supported in the custom format.
- Integer literals can now be parsed directly, removing the need to go through IntegerAttr.
- The inliner is gaining support for custom simplification pipelines.
- FrozenRewritePatternList is now copyable, with each copy sharing the same internal pattern list.
Optimizations and Code Generation
- Vector dialect improvements for architectural-specific features:
- Fixed composition and code duplication issues by making AVX512 lowering a âsubpassâ of architectural-neutral vector dialect lowering
- More architectural-specific vector dialects are being added using same approach: ArmNeon and ARMSVE
- Allows mixing arbitrary architectural-specific dialects with the architectural-neutral vector dialect, for your AVX512-enabled ARMNeon optimized processor
- ArmNeon dialect has landed. Discussion ongoing to automate op creation as possible.
- Linalg on tensors: tile-and-fuse on tensors in progress. IREE and XLA starting to experiment with the approach.
- Sparse compiler progress
- Added reduction âscalarizationâ feature, which avoids loading/adding/storing from buffers in an innermost chain of for-loops
- Made minor improvements (mark tensor indices as sparse/dense/undef, pre-compute simplifications rather than doing it repeatedly during codegen)
- This prepares the next planned feature: vectorization
Other
In the Ecosystem
CIRCT : Circuit IR Compilers and Tools aka âMLIR for hardwareâ
- Handshake dialect updates to merging and branching ops are done.
- This means these ops can all be emitted as System Verilog now, closing a long-standing issue.
- Infrastructure for equivalence checking using yosys has landed.
- cmake exports for projects that depend on CIRCT has landed
- A number of patches improving modeling of SystemVerilog interfaces have landed.
TensorFlow / MLIR-HLO
Progress on XLA GPU backend:
- GEMM and Conv migrated to take LMHLO.
- Reduce is fully migrated to take LMHLO.
- All elementwise ops are migrated to take LMHLO.
Kernel Generator Project:
- Use linalg on tensors for fusion now.