Conditional/ternary operator in RTL or SV?

amaleewilson · February 9, 2021, 9:24pm

There doesn’t seem to be support for the conditional/ternary operator in Verilog in either the RTL or SV dialects.

Is there another way to express the following outside of an always block?
assign A = condition ? B : C

My understanding is that you can’t/don’t put if/else outside of an always block.

I’d be happy to add this op if there’s interest, but wasn’t sure if its absence is deliberate.

mikeurbach · February 9, 2021, 9:39pm

Is the RTL MuxOp what you’re looking for?

github.com

llvm/circt/blob/357db318c177428824dae446c166b7867f6b6ed2/include/circt/Dialect/RTL/RTLCombinatorial.td#L259


  let builders = [
    OpBuilderDAG<(ins "ValueRange":$inputs)>,
    OpBuilderDAG<(ins "Value":$lhs, "Value":$rhs), [{
      return build($_builder, $_state, ValueRange{lhs, rhs});
    }]>
  ];
}
// Select one of two values based on a condition.
def MuxOp : RTLOp<"mux",
 [NoSideEffect, AllTypesMatch<["trueValue", "falseValue", "result"]>]> {
  let summary = "Return one or the other operand depending on a selector bit";
  let description = [{
    ```
      %0 = mux %pred, %tvalue, %fvalue : i4
    ```
  }];
  let arguments = (ins I1:$cond, RTLNonInOutType:$trueValue,
                       RTLNonInOutType:$falseValue);

amaleewilson · February 9, 2021, 11:02pm

Oops, I had forgotten what a mux is.Thank you!