There doesn’t seem to be support for the conditional/ternary operator in Verilog in either the RTL or SV dialects.
Is there another way to express the following outside of an always block?
assign A = condition ? B : C
My understanding is that you can’t/don’t put if/else outside of an always block.
I’d be happy to add this op if there’s interest, but wasn’t sure if its absence is deliberate.