I’m sorry about that I proposed a stupid question It seems that llhd use the outside synthesis tool to generate the synthesized netlists and they represent the synthesized netlists with llhd ir, that is magic for me and I still need to keep studying more about their process.
Actually any forms of netlist is ok, netlist is just a description level of circuit and we can describe it in form of verilog, but mostly in form of BLIF、AIG.
Currently, each design automation tool lowers HDLs to its own IR and these tools are monolithic and mostly proprietary. So what I expect is that the design of mlir can be used in the whole ic design’s workflow instead of just frontend, at least to the synthesized netlists level. And that is not so difficult from my perspective, and I have no questions, Thank you for your reply! : )