I (maybe mistakenly) recall that some folks were using sv.verbatim to print non-Verilog collateral that required the final Verilog names for modules and ports. Specifically, I’m looking to generate a C++ test harness for Verilator, which needs to know the name of the top module and its ports.
I don’t see a way of doing this as part of ExportVerilog… can someone point me in the right direction? My fallback plan is just to add a crazy prefix like //>>GEORGE'S FILE>> and filter the output on that, but that feels quite fragile and hacky.
Thanks @seldridge for showing me the relevant code here: circt/EmitOMIR.cpp at main · llvm/circt · GitHub
It looks like you can provide an output_file attribute to the verbatim op. In order for this to do anything, however, you need to use the export-split-verilog pass, which outputs directly to a directory unlike export-verilog. This works for my use case but also means if you want to get split output without writing to the file system you may need to write a custom pass.
This is what we ended up doing for the Tcl export. We have just leaned in to writing split files out to the file system. @jdd and I briefly discussed what it might look like to handle split outputs without writing to the file system, but ultimately didn’t open that can of worms, since splitting up the outputs for a large design is much nicer for our use-case anyway.
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Can you point to the code you use for this for reference?
We build up a string of Tcl, using InnerRefAttrs to refer to instances, and stuff it into a VerbatimOp here: circt/ExportQuartusTcl.cpp at main · llvm/circt · GitHub. We have a way to attach an output_file attribute there as well. Hope that helps, and let me know if you have any questions on this stuff. I need to go review the docs and see if there is anything to add… I just learned how to do this in the last weeks.
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