Hi all,
Recently, the CIRCT folks have been discussing the best way to support type declarations and type aliases in our IRs. One motivation is a desire to output typedef System Verilog statements, which give a name to a (potentially complicated) type and make the output more concise and human readable. The tip of the iceberg here is: how to represent such a “type declaration” in the IR, as well as how to refer to those in the type system.
We have circled back to this topic several times in the CIRCT ODMs, and had some interesting discussions covering a range of design points. We are hoping to involve the broader MLIR community, as this is a pretty core topic and nothing about it is specific to hardware.
Would this topic be of interest at a future ODM? I’m happy to put together a short presentation with more details in order to seed a discussion.