Are there any plans to have a non-verilog backend ? I wonder if it would be interesting to have a more low-level output. Some examples I’m thinking of:
From the HW Dialect straight to yosys’s JSON format Yosys Open SYnthesis Suite :: Command Reference :: write_json , which can then be fed into yosys.
From HW dialect straight to a more structural description with detailed placement and resources information when targetting FPGA, as described in this paper: https://homes.cs.washington.edu/~vegaluis/pubs/pldi21_vega_reticle.pdf