LLVM Discussion Forums

SystemVerilog fragments

A requirement for ESI is the ability to integrate deeply with existing SV code. Like be able to produce a SystemVerilog fragment to be `included in some SV code. ESI would have to be able to reason about modules already instantiated in the SystemVerilog and connect up to their ports.

I was thinking of adding two Ops: a region called fragment and one called externModule. The former to indicate that this region will become a SV fragment. Presumably, this will signal to whatever is writing the SV that the module/endmodule are to be skipped. The latter is to reason about the necessary properties of an already-instantiated module in the existing SV code. In particular, it would contain ESI ports which the module has as arguments and results.

Does this make sense? If so, in which dialect should it go? It could go in ESI but this seems more general than just ESI.

@jdd here’s the op I mentioned for SV “textual values”: https://github.com/llvm/circt/blob/master/include/circt/Dialect/SV/Expressions.td#L7. Is that what you were looking for?

This is like “inline assembly” for system verilog. I think this makes sense to support as part of the SV dialect, but i’d encourage you to look at inline assembly in LLVM IR. We should have answers for the same sorts of problem it has: you want to be able to refer to value names outside the scope, and those need to be substituted into the text of the “asm” blob etc.

Not quite. I’m looking for a region which contains Ops from SV and RTL dialects (and, presumably, others) but when emitVerilog outputs the textual SystemVerilog it just doesn’t encapsulate it in module foo(); ... endmodule. I think that’s sufficient. Maybe this should just be operations not contained in rtl.module…?