Question about register dependency in llvm-mca

Recently I am working on llvm-mca. I tested a code block with simple data dependency, but it seemed wrong on the timeline-view. The code was tested with aarch64 architecture and

Index     0123456789
[0,0]     DeeeeER  .   ldr      w8, [sp, #8]
[0,1]     D====eeER.   add      w8, w8, w9
[0,2]     D======eER   str      w8, [sp, #8]
[0,3]     DeeeeE---R   ldr      w8, [sp, #8]

a ldr instruction is after a str instruction and they access the same memory address, but it seems that ldr is executed before str. Is that right?