Hi all, I am new to the CIRCT project and I am currently encountering some problems simulating my system verilog code using llhd-sim.
I have reduced the verilog to a multiply between 2 constants, and the converted llhd seems simple
llhd.entity @adder(%clk: !llhd.sig, %res: !llhd.sig) → (%i5_output: !llhd.sig ) {
%0 = llhd.const #llhd.time<0s, 0d, 1e> : !llhd.time
%1 = llhd.const 16 : i32
llhd.drv %i5_output, %1 after %0 : !llhd.sig
}
yet the llhd-sim shows the following error:
Assertion failed: (idx < size()), function operator[], file …/llvm/llvm/include/llvm/ADT/SmallVector.h, line 277.
PLEASE submit a bug report to https://bugs.llvm.org/ and include the crash backtrace.
Stack dump:
0. Program arguments: …/build/bin/llhd-sim addersvllhd.mlir -n 10 -r adder
Stack dump without symbol names (ensure you have llvm-symbolizer in your PATH or set the environment var LLVM_SYMBOLIZER_PATH to point to it):
0 libcirct-llhd-signals-runtime-wrappers.dylib 0x000000011dca593d llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) + 61
1 libcirct-llhd-signals-runtime-wrappers.dylib 0x000000011dca5eeb PrintStackTraceSignalHandler(void*) + 27
2 libcirct-llhd-signals-runtime-wrappers.dylib 0x000000011dca3a6b llvm::sys::RunSignalHandlers() + 123
3 libcirct-llhd-signals-runtime-wrappers.dylib 0x000000011dca83f8 SignalHandler(int) + 232
4 libsystem_platform.dylib 0x00007fff6af445fd _sigtramp + 29
5 libdyld.dylib 0x00007fff6ad4a78f dyldGlobalLockRelease() + 0
6 libsystem_c.dylib 0x00007fff6ae1a808 abort + 120
7 libsystem_c.dylib 0x00007fff6ae19ac6 err + 0
8 libcirct-llhd-signals-runtime-wrappers.dylib 0x000000011db4fa48 llvm::SmallVectorTemplateCommon<circt::llhd::sim::Signal, void>::operator[](unsigned long) + 104
9 libcirct-llhd-signals-runtime-wrappers.dylib 0x000000011db4f912 driveSignal + 178
10 libcirct-llhd-signals-runtime-wrappers.dylib 0x000000011e1240f1 driveSignal + 6113425
11 llhd-sim 0x000000010acda78e main + 1518
12 libdyld.dylib 0x00007fff6ad4bcc9 start + 1
My command to llhd-sim is -n 10 -r adder and I think the expect behaviour should be a constant signal at the output (although I am not sure since the simulation failed).
I was able to trace the code till line 235 of engine.cpp and I am using a mac with latest OS. Any help would be greatly appreciated!!!
(ps: this is not the full code for my sv; I have reduced it to the simplest form to see if I can get an output; originally my code just aborted when the reaches the adder.adder entity in state…)