As we are wrapping up the lowerings for the various Handshake ops, @hanchenye mentioned we should probably have a strict verification for each of the components in this issue: [HandshakeToFIRRTL] Lowering of MemoryOp/LoadOp/StoreOp · Issue #337 · llvm/circt · GitHub.
We thought we’d open up a thread for discussion here to see if anyone in the community has some feedback.
My two cents is it might be worth creating an integration test, similar to ESI, that runs all the lowerings to FIRRTL, then runs the FIRRTL lowerings to System Verilog, and checks the output using Verilator.
The upside is this lets us verify the hardware we are generating does in fact have the properties we care about (latency insensitive, etc.).
The downside is we are testing the FIRRTL lowering path as well. Since this is a functional test, hopefully changes to the FIRRTL implementation don’t break it (too often).
What do others think about testing Handshake at the RTL level?