Expressing Verilog typedefs in MLIR

Have we thought about how typedefs are expressed/inferred when exporting Verilog from MLIR? MLIR has aliases but I haven’t yet figured out how they are represented programmatically and I’m not sure if they are meant to carry information (as opposed to being equivalent to writing out the full type in all cases).

Yes. The plan is to create a typedef op once struct output has landed. I was thinking ExportVerilog would create a mapping of Type to typedef ops and use the typedef whenever it encounters the typedef’d type.

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A typedef op makes sense to me. Would it define a symbol or something else?

Yes. But it would also require a Type → Symbol mapping, and hierarchically since typedefs can appear within modules as well. (Thus my recent PR to deal with names which is similar in structure to this.)