I am interesting about pre-RA-scheduler pass of llc. I have seen that I this flags has different instruction schedulers availables:
–pre-RA-sched= - Instruction schedulers available (before register allocation):
=list-ilp - Bottom-up register pressure aware list scheduling which tries to balance ILP and register pressure
=list-hybrid - Bottom-up register pressure aware list scheduling which tries to balance latency and register pressure
I need to find documentation on how the details of the implementations of these schedulers are, some examples of code with the transformations that they execute, etc.
I checked the files of LLVM that implements this passes, but I didn’t find information.
Somebody can help me?