Having to pass around
rstn like they’re just normal wires is one of the many pet peeves I have with SystemVerilog. I don’t want to repeat it in the RTL dialect – there must be a better way.
Clocks and resets are not normal wires
Of course, they are just very high fan-out wires which have to go everywhere. They differ from “normal” wires which carry signals significantly:
- They are needed virtually everywhere! All (standard) sequential logic needs them. They make virtually no difference at the functional level except to cause bugs.
- Synthesis engines need to recognize them and treat them specially. ASIC synthesis engines have significant complexity in designing clock trees. FPGA synthesizers need to map them to special clock networks. I’m not sure what – specifically – they do for reset logic but it’s my understanding that if you do a poor job designing your reset logic, your timing performance will suffer.
- As a result of the above, you really don’t want to mess with the clock signal. It’s a rookie mistake to muck with a clock signal (e.g. naïvely divide it). Many people have gotten burned by tools not recognizing their custom logic on clocks. FPGAs (at least) have hardened circuitry to work with clocks which designers should pretty much always be using.
Designers (esp. ASIC/SoC designers) think of things like clock domains, reset domains, and power domains. While the power domain is out-of-scope for CIRCT (at least for now), it provides a good model: it is implicitly everywhere and special logic needs to be added at the boundaries of different power domains (e.g. situations where one domain was off but is powering up, different voltages, etc.)
Explicit clock and reset domains
I propose that we create an explicit notion of clock and reset domains.
The model should be a symbol so we don’t have to pass it around everywhere. Operations can have an attribute which specifies the symbol of the clock and reset domains to which it is assigned. Said attributes should be inherited. No more clock and reset arguments!
Clock and reset domain relationship
We cannot assume that clock and reset domains will always be the same as it is common to reset one part of a design separately from the others regardless of the clock domains in which they reside. However, given that resets are often synchronously de-asserted (and really should always be to avoid metastability), it is reasonable to model a reset domain as belonging to a clock domain.
I think we should model clock domains as a flat set and a tree of reset domains under each one. This won’t cover all possible cases but it should cover the most common cases.