Hi all (and apologies if this is in the wrong group),
I’m working with a new and somewhat unusual target: it has very limited general purpose registers (3), nearly unlimited memory (but each memory address can only be written once), and instead of working on bits, it works on a large prime field. Without going into details, it can do things such as work on bits, with help from an “advisor,” but it is less efficient. Now, I’d like to be able to compile a higher-level language to this ISA so that I and others can more easily write software targeting it. As I don’t have much experience with LLVM, I am not sure how difficult writing a backend targeting this ISA would be. As an alternative, I also imagined having the higher-level language compile to a RISC architecture (such as ARMv7), and then writing a compiler of my own (along with a runtime) to compile the ARM code into this ISA. Does this sound like a more straightforward task than writing a new LLVM backend?
Thanks, and let me know if any additional information would help.