About the LLVM Incubator category
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0
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78
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August 21, 2020
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[CFP] Languages, Tools, and Techniques for Accelerator Design
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0
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36
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February 23, 2021
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Expressing Verilog typedefs in MLIR
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3
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51
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February 21, 2021
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Missing LLHD symbol preventing updating MLIR
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1
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41
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February 10, 2021
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Conditional/ternary operator in RTL or SV?
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2
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38
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February 9, 2021
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Please use 'main' instead of 'master'
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2
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145
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February 8, 2021
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Representing device data
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11
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142
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February 7, 2021
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Weekly meeting videos
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0
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60
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January 27, 2021
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[npcomp] Adding padding support for conv2d
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8
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168
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January 22, 2021
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Proposal for DeMux ops and RSink ops in Handshake
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8
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67
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January 20, 2021
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Calyx talk and next steps
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4
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125
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January 20, 2021
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[RFC] One-connect semantics for RTL
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2
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65
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January 15, 2021
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Support for floating/fixed/etc. types
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6
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75
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January 14, 2021
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FIRRTL Dialect back to FIRRTL
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5
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102
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January 14, 2021
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HandshakeToFIRRTL verifications
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6
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71
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January 13, 2021
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Should `rtl.add i1, i1` return i1 or i2?
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9
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144
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January 10, 2021
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FIRRTL dialect rationale doc
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4
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147
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January 8, 2021
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Video from the talk today
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2
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119
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January 7, 2021
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SV/RTL dialect rationale
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2
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76
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January 7, 2021
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Clock and reset domains in the RTL dialect
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4
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71
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January 5, 2021
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Type Inference in RTL
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9
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144
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January 2, 2021
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Errors while building LLVM for CIRCT
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2
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58
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December 21, 2020
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Simulation test pipelines (non-Verilator)
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11
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174
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December 19, 2020
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Lowering memref and load/store from Handshake to FIRRTL
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3
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87
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December 18, 2020
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Simulating RTL with LLHD
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3
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84
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December 17, 2020
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Richard Townsend's talk today
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0
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79
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December 16, 2020
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Canonical way to create back edges
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5
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71
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December 16, 2020
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Getting the size of a type in SystemVerilog
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0
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45
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December 15, 2020
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Type of operands as the arguments of fold functions?
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1
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53
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December 11, 2020
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CIRCT as a backend for npcomp
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24
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363
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December 10, 2020
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